In a so-called multi chip module technology, a plurality of semiconductor chips are mounted on such a mounting substrate as to have a plurality of internal wirings and a plurality of external terminals. The plurality of semiconductor chips and the mounting substrate are brought into an integrated device. Electrical connections between the semiconductor chips and external terminals, and electrical connections mutually necessary for the plurality of semiconductor chips are done by internal wirings in the mounting substrate. A multi chip module constituted as an integral or one semiconductor device is tested if it has required functions.
The invention related to a bare chip failure detecting device for a multi chip module has been disclosed in Japanese Unexamined Patent Publication No. Hei 8 (1996)-334544. According to the invention described in the same publication, a bare chip and a package chip having the same logic structure as the bare chip are mounted on a test board. A decision as to whether or not the bare chip is good, is performed by a comparison between both output signals. Described more specifically, the technology disclosed in the same publication intends to disable others of a plurality of package chips and a plurality of bare chips except for ones thereof, and compare signals of both chips associated with each other to thereby specify a defect in bare chip (it is called a prior art 1).
One wherein semiconductor chips mounted in a multi chip module are respectively provided with structures for individually supplying a power supply thereto, and only the semiconductor chips to be tested are individually tested by supplying the power supply to the semiconductor chips alone, has been proposed in Japanese Unexamined Patent Publication No. 2000-111617 (it is called a prior art 2).
There has been proposed in Japanese Unexamined Patent Publication No. 2000-22072 and Japanese Unexamined Patent Publication No. Hei 5 (1993)-13662, one wherein a multi chip module is provided with an input path and an output path for testing and has terminals for performing switching between the paths upon the normal operation and testing, and the function of performing switching between the input path and output path for the testing and normal operation is provided within a chip constituting the multi chip module, or a multi chip module is newly added as a chip constitutive of the multi chip module (it is called a prior art 3).
Advances in semiconductor technology are now creating the orientation of a technology which intends to constitute a plurality of semiconductor chips for constituting an electronic system, like a chip for microcomputer, a DRAM chip, and a flash memory chip as a semiconductor device configured in one package form as a whole.
Namely, when a plurality of semiconductor devices are used wherein individual semiconductor chips rather than a plurality of semiconductor chips are packaged by a normal package technology such as a technology for QFP (Quad Flat Package), CSP (Chip Size Package or Chip Scale Package), or BGA (Ball Grid Array), and they are implemented on a mounting substrate like a printed board, decreasing the distance between the semiconductor chips and their wiring distances becomes difficult, and hence a signal delay due to wiring increases, thus causing restrictions in the speeding up and downsizing of each device.
On the other hand, in a multichip (Multi Chip Module) technology, a plurality of semiconductor chips significantly brought into small form, each of which is referred to as a so-called bare chip, are formed as a semiconductor device configured in one package form. Therefore, the wiring distance between the respective chips can be shortened, and the characteristic of the semiconductor device can be enhanced. Bringing a plurality of chips to one package makes it possible to bring a semiconductor device into less size and decrease its mounting areas to thereby scale down the semiconductor device.
It is desirable that as in, for example, a microcomputer chip, and a DRAM or rush memory chip connected to such microcomputer chip, ones closely associated with one another are selected as semiconductor chips for constituting a multi chip module. When such combinations of plural semiconductor chips closely associated with one another are selected, the characteristic of the multi chip module can be fully utilized. It is desirable that both a test on the function of such a whole multi chip module and a test on each individual chip itself can be carried out.
However, the prior arts 1 through 3 do not pay any attention to the characteristic of the multi chip module referred to above and gives consideration only to exclusively operating the individual chips independently. In the prior art 1, for example, neither of the operation of only the microcomputer chip at the operation that when the microcomputer chip is operated, a memory circuit responds to it, and a complex test on the accessing of the microcomputer chip to a built-in memory circuit can be carried out.
Since the power supply is distributed in the prior art 2, the prior art 2 still gives consideration only to independent tests on the individual semiconductor chips. In addition, the prior art 2 do not pay attention to a signal leak developed via each semiconductor chip supplied with no operating voltage and is not capable of determining whether a semiconductor chip intended for testing is defective or it is faulty due to a signal leak developed via a power-off semiconductor chip. Besides, the prior art 2 has the fear that since the power supply for the respective semiconductor chips is separately supplied thereto during the normal operation, a small potential difference in power supply voltage between the semiconductor chips results in an offset upon the transfer of a signal between the semiconductor chips, and reflection-based noise occurs in a signal transferred across a power cutoff portion to thereby deteriorate noise resistance at a high-speed operation, thus bringing about an adverse effect that impairs an original merit of a multi chip module.
Even the prior art 3 still has a problem in that it pays attention only to independent tests on the individual semiconductor chips, and a substantial increase in external terminal occurs, and the period and cost necessary to develop novel chips increase, or the chips constituting the multi chip module increase due to the addition of the chips each having the function of switching between the input path and the output path, thus resulting in an increase in manufacturing cost.
An object of the present invention is to provide a semiconductor device which enables a high-reliability test while maintaining the performance of a multi chip module, and its test method. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.